ISYS-Projekt ?Signalintegrit?t“
"Simulation models for components of fast digital circuits"
Project participants::
Dipl.-Ing. (FH) H. Turan
Dipl.-Ing. (FH) G. Hüdepohl
Prof. Dr.-Ing. H. Diestel
"Simulation models for components of fast digital circuits"
Project participants::
Dipl.-Ing. (FH) H. Turan
Dipl.-Ing. (FH) G. Hüdepohl
Prof. Dr.-Ing. H. Diestel